Hardware reverse engineering for IC Circuitry Analysis is a multi-stage process that includes sample preparation, SEM imaging, image processing and vectorization, circuit extraction and analysis. As modern technology shrinks die feature sizes and increases the number of it metallization layers, it significantly complicates not only the sample preparation and imaging, but also greatly increases the volume of data to be processed at circuit extraction.

When processing large areas of ICs with advanced technology nodes, it is extremely difficult to locate and mitigate the errors caused by artefacts and other process inaccuracies which lead to the appearance of false contacts, phantom short circuits, or wire interruptions. The presentation addresses the method to reduce these errors while accelerating and improving reliability of their identification and handling.

During circuitry extraction the processing of large areas of the die generates a significant amount of geometric data obtained via vectorization; to simplify and accelerate subsequent analysis, respective vectorized data optimization techniques are applied. The presentation will also explore specific applications of AI, as well as opportunities to considerably reduce cycle time for extracting circuits from both digital and mixed-signal blocks.