As hardware increasingly serves as the root of trust in modern computing systems, Hardware Reverse Engineering (HRE) has become a foundational capability for security assurance. HRE underpins critical security tasks such as design verification, supply-chain assurance, and vulnerability discovery in Integrated Circuits (ICs) and Field Programmable Gate Arrays (FPGAs). Despite its importance, knowledge in this domain remains fragmented across research communities, each shaped by distinct threat models, assumptions, and evaluation practices. In this talk, we present a systematization of knowledge based on an in-depth analysis of 195 peer-reviewed publications identified through a systematic literature review. Our analysis characterizes the technical methods employed throughout the HRE workflow, spanning IC, FPGA, and netlist-level reverse engineering. We also assess the availability, usability, and reproducibility of 33 published research artifacts using established artifact evaluation criteria, providing insight into the practical reproducibility of prior work. Beyond technical methods, we identify key challenges that impede progress in HRE , including the lack of standardized benchmarks and evaluation metrics, insufficient recognition of foundational tools, datasets, and infrastructure, and legal and ethical constraints affecting research and dissemination. Based on these findings, we provide guidance for researchers and practitioners and outline directions aimed at fostering sustained progress in the Hardware Reverse Engineering community.